Guías-E

1. General information

Course:

VLSI DESIGN

Code:

42373

Type:

ELECTIVE

ECTS credits:

6

Degree:

407 - DEGREE PROGRAMME IN COMPUTER SCIENCE ENGINEERING

Academic year:

2022-23

Center:

108 - SCHOOL OF COMPUTER SCIENCE OF C. REAL

Group(s):

20

Year:

4

Duration:

C2

Main language:

Spanish

Second language:

English

Use of additional languages:

English Friendly:

Y

Web site:

Bilingual:

N

Lecturer: JESUS SALIDO TERCERO - Group(s): 20

Building/Office

Department

Phone number

Email

Office hours

Fermín Caballero/2.18

INGENIERÍA ELÉCTRICA, ELECTRÓNICA, AUTOMÁTICA Y COMUNICACIONES

3745

jesus.salido@uclm.es

Available at https://esi.uclm.es/index.php/grado-en-ingenieria-informatica/profesorado/

2. Pre-Requisites

To take this course it is advisable to have completed the Basic Training modules (Module I) and the module common to the Computing Branch (Module II).

This subject supports and complements the competences and knowledge acquired in the subjects:

Computer Technology,
Computer Structure,
Design of Microprocessor-based Systems, and
Embedded Systems

3. Justification in the curriculum, relation to other subjects and to the profession

This subject is integrated into the Complementary Training Optional Module.

4. Degree competences achieved in this course

Course competences
Code	Description
IC01	Ability to design and build digital systems, including computers, based on microprocessors and communication systems.
INS01	Analysis, synthesis, and assessment skills.
INS04	Problem solving skills by the application of engineering techniques.
PER04	Interpersonal relationship skills.
SIS01	Critical thinking.
SIS03	Autonomous learning.
SIS05	Creativity.
UCLM03	Accurate speaking and writing skills.

5. Objectives or Learning Outcomes

Course learning outcomes
Description
Knowledge and experience in the use of the characteristics of the development platforms for mobile systems and an ability to design applications and services on them.
Ability to design specific-purpose hardware from a functional description of the system, respecting the imposed performance and cost requirements.
An understanding of how technology has evolved in engineering and particularly in computers, such that it will allow the interpretation and analysis of future innovations.
Additional outcomes
Description
Be able to apply a methodology of digital circuit design from description and simulation to final implementation. Be able to develop embedded systems using programmable logic using the VHDL hardware description language.

6. Units / Contents

Unit 1: Introduction to logic cicuits.
Unit 2: Implementation technology.
Unit 3: Optimized implementation of logic functions.
Unit 4: Number rerpresentation and arithmetic circuits.
Unit 5: Building blocks for combinational circuits.
Unit 6: Flip-flops, registers and counters.
Unit 7: Syncronous Sequential Circuits.

7. Activities, Units/Modules and Methodology

Training Activity	Methodology	Related Competences	ECTS	Hours	As	Com	Description
Class Attendance (theory) [ON-SITE]	Lectures	IC01	0.72	18	N	N	Presentations by the teacher at class (LEC)
Individual tutoring sessions [ON-SITE]		IC01 PER04 SIS01	0.18	4.5	N	N	Individual or small group tutoring in the teacher's office, class or laboratory (TUT)
Study and Exam Preparation [OFF-SITE]	Self-study	IC01 INS01 INS04 SIS01 SIS03 UCLM03	2.1	52.5	N	N	Individual Study (STU)
Other off-site activity [OFF-SITE]	Practical or hands-on activities	IC01 INS01 INS04 PER04 SIS01 SIS03 SIS05 UCLM03	0.6	15	N	N	Laboratory Practice Preparation (LAB-P)
Problem solving and/or case studies [ON-SITE]	Problem solving and exercises	IC01 INS01 INS04 SIS01 SIS05 UCLM03	0.6	15	Y	N	Solving exercises by the teacher and students (EXE)
Writing of reports or projects [OFF-SITE]	Self-study	IC01 INS01 INS04 SIS01 SIS03 SIS05 UCLM03	0.9	22.5	Y	N	Writing a report on a topic proposed by the teacher (REP)
Laboratory practice or sessions [ON-SITE]	Practical or hands-on activities	IC01 INS01 INS04 PER04 SIS01 SIS05 UCLM03	0.6	15	Y	Y	Completion of the programmed practices in the laboratory (LAB)
Final test [ON-SITE]	Assessment tests	IC01 INS01 INS04 SIS01 SIS05	0.3	7.5	Y	Y	Completion of a final exam of the entire syllabus of the subject (EXA)
Total:			6	150
Total credits of in-class work: 2.4			Total class time hours: 60
Total credits of out of class work: 3.6			Total hours of out of class work: 90

As: Assessable training activity
Com: Training activity of compulsory overcoming (It will be essential to overcome both continuous and non-continuous assessment).

8. Evaluation criteria and Grading System

Evaluation System	Continuous assessment	Non-continuous evaluation *	Description
Final test	50.00%	50.00%	Compulsory and recoverable activity to be carried out on the scheduled date for the final examination of the ordinary call.
Theoretical papers assessment	15.00%	15.00%	Non-compulsory and recoverable activity to be carried out before the end of the teaching period.
Laboratory sessions	25.00%	25.00%	Compulsory and recoverable activity to be carried out on the scheduled date for the final examination of the ordinary call.
Assessment of active participation	10.00%	10.00%	Non-compulsory and recoverable activity. To be carried out in the theory / laboratory sessions for students of the continuous modality. Non-continuous students will be evaluated for this activity through an alternative system in the ordinary exam.
Total:	100.00%	100.00%

According to art. 4 of the UCLM Student Evaluation Regulations, it must be provided to students who cannot regularly attend face-to-face training activities the passing of the subject, having the right (art. 12.2) to be globally graded, in 2 annual calls per subject , an ordinary and an extraordinary one (evaluating 100% of the competences).

Evaluation criteria for the final exam:

Continuous assessment:

In compulsory activities, a minimum mark of 40% is required in order to pass that activity and have the possibility to therefore pass the entire subject. The evaluation of the activities will be global and therefore must be quantified by means of a single mark. In the case of the activities that may be retaken (i.e., rescheduling), an alternative activity or test will be offered in the resit/retake exam call (convocatoria extraordinaria).

The final exam will be common for all the theory/laboratory groups of the subject and will be evaluated by the lecturers of the subject in a serial way, i.e., each part of the final exam will be evaluated by the same lecturer for all the students.

A student is considered to pass the subject if she/he obtains a minimum of 50 points out of 100, taking into account the points obtained in all the evaluable activities, and also has passed all the compulsory activities.

For students who do not pass the subject in the final exam call (convocatoria ordinaria), the marks of activities already passed will be conserved for the resit/retake examcall (convocatoria extraordinaria). If an activity is not recoverable, its assessment will be preserved for the resit/retake exam call (convocatoria extraordinaria) even if it has not been passed. In the case of the passed recoverable activities, the student will have the opportunity to receive an alternative evaluation of those activities in the resit/retake exam call and, in that case, the final grade of the activity will correspond to the latter grade obtained.

The mark of the passed activities in any call, except for the final exam, will be conserved for the subsequent academic year at the request of the student, provided that mark is equal or greater than 50% and that the activities and evaluation criteria of the subject remain unchanged prior to the beginning of that academic year.

The failure of a student to attend the final exam will automatically result in her/him receiving a "Failure to attend" (no presentado). If the student has not passed any compulsory evaluation activity, the maximum final grade will be 40%.
Non-continuous evaluation:

Students may apply at the beginning of the semester for the non-continuous assessment mode. In the same way, the student may change to the non-continuous evaluation mode as long as she/he has not participated during the teaching period in evaluable activities that together account for at least 50% of the total mark of the subject. If a student has reached this 50% of the total obtainable mark or the teaching period is over, she/he will be considered in continuous assessment without the possibility of changing to non-continuous evaluation mode.

Students who take the non-continuous evaluation mode will be globally graded, in 2 annual calls per subject, an ordinary and an extraordinary one (evaluating 100% of the competences), through the assessment systems indicated in the column "Non-continuous evaluation".

In the "non-continuous evaluation" mode, it is not compulsory to keep the mark obtained by the student in the activities or tests (progress test or partial test) taken in the continuous assessment mode.

Specifications for the resit/retake exam:

Evaluation tests will be conducted for all recoverable activities.

Specifications for the second resit / retake exam:

Same characteristics as the resit/retake exam call.

9. Assignments, course calendar and important dates

Not related to the syllabus/contents
Hours	hours

General comments about the planning:

The subject is taught in 3 x 1,5 hour sessions per week.

10. Bibliography and Sources

Author(s)	Title	Publishing house	ISBN	Year	Description	Link
Brock J. LaMeres	Introduction to Logic Circuits & Logic Design Using VHDL, 2nd. Ed.	Springer	978-3-030-12488-5	2019	This book addresses the lower-level foundational void by providing a comprehensive, bottoms-up coverage of digital systems. The book begins with a description of lower-level hardware including binary representations, gate-level implementation, interfacing, and simple combinational logic design. Only after a foundation has been laid in the underlying hardware theory is the VHDL language introduced. The VHDL introduction gives only the basic concepts of the language in order to model, simulate, and synthesize combinational logic.	https://doi.org/10.1007/978-3-030-12489-2
Intel	Quartus Prime Introduction Using VHDL Designs	Intel		2017	Lab manual.
Stephen E. Brown and Zvonko Vranesic	Fundamentals of Digital Logic with VHDL Design 3rd. ed.	McGraw-Hill	978-007-126880-6	2009	Theory and exercises.
Stephen E. Brown y Z. Vranesic	Fundamentos de Lógica Digital con Diseño VHDL 2ª Ed.	McGraw-Hill	970-10-5609-4	2006	Teoría y problemas.
Terasic - Altera	DE0-Nano User manual	Terasic		2013	Lab manual.	https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593&PartNo=4
Thomas L. Floyd	Digital fundamentals : a systems approach.	Pearson Educación	978-0-13-293395-7	2013	Only for deeper knowledge on logic systems fundamentals.
Thomas L. Floyd	Fundamentos de Sistemas Digitales, 11ª ed.	Pearson Educación	978-84-9035-300-4	2016	Sólo consultas de temas básicos de sistemas digitales.